Recently, a main issue for developing a semiconductor memory device is changed from integration scale to operation speed. Synchronous semiconductor memory devices such as a double data rate synchronous dynamic random access memory (DDR SDRAM) or a RAMBUS DRAM comes into the spotlight for a high speed semiconductor memory device.
The synchronous semiconductor memory device performs an operation in synchronization with a system clock. A SDRAM is considered as a mainstream in a memory market for a synchronous memory device. The SDRAM performs an operation for a data access in response to rising edge of the system clock. The SDRAM performs one data access every one cycle of the external system clock. Alternatively, the DDR SDRAM performs an operation for a data access in response to rising edge and falling edge of the system clock. The SDRAM performs two data accesses every one cycle of the external system clock.
Generally, the system clock is used as a reference signal for performing operation or adjusting or controlling operating timing in a system or a circuit including semiconductor devices. Also, the system clock is used as a reference signal to guarantee a high-speed operation without error.
When internal circuits of a semiconductor memory device use an external system clock input, the system clock is transferred to the internal circuits with delay, i.e. clock skew, caused by the clock transmission path. To compensate the delay, a synchronizing circuit such as a phase locked loop (PLL) or a DLL are widely used in a semiconductor memory device. Since the DLL has a greater advantage for noise than the PLL, the DLL is broadly used in the synchronous semiconductor memory device including the DDR SDRAM. The DLL in the synchronous semiconductor memory device receives a system clock and compensates a clock skew caused by a clock path in the semiconductor memory device to synchronize an output timing of a data with the transition of the system clock.
FIG. 1 is a block diagram of a delay locked loop (DLL) in a conventional DDR SDRAM.
As shown, the delay locked loop includes first and second clock buffers 110 and 120, first and second delay lines 130 and 140, a phase comparator 170, a delay line controller 180, a delay model circuit 190, and first and second DLL buffers 150 and 160.
The first clock buffer 110 receives a clock bar signal/CLK to generate a first internal clock fclkt2 in response to a clock enable signal cke, and the second clock buffer 120 receives a clock signal CLK to generate a second internal clock rclkt2. The first internal clock fclkt2 is input to the first delay line 130 and the second internal clock rclkt2 is input to the second delay line 140, respectively.
The delay model circuit 190 delays an output of the second delay line 140 by a predetermined amount estimated from a clock path and data path where data or the clock signal passes on in the semiconductor memory device. The phase comparator 170 compares phases of the second internal clock rclkt2 and output of the delay model circuit 190. The delay line controller 180 determines each delay amount of the first and second delay lines 130 and 140 in response to the comparison result of the phase comparator 170.
Output of the first delay line 130 is input to the first DLL driver 150 and supplied to the semiconductor memory device as a first DLL clock fclk_dll. Likewise, output of the second delay lines 140 is input to the second DLL driver 160 and supplied as a second DLL clock rclk_dll.
The delay model circuit 190 includes a dummy clock buffer, a dummy output buffer, a dummy load, and the like in order to implement a delay condition that is the same as a clock path in the semiconductor memory device. Generally, the delay model circuit 190 is known as a replica circuit.
Hereinafter, detailed operation of the DLL for use in the conventional DDR SDRAM is described.
First, the first clock buffer 110 receives a rising edge of the clock bar signal/CLK to generate the first internal clock fclkt2, and the second clock buffer 120 receives a rising edge of the clock signal CLK to generate the second internal clock rclkt2. Herein, the first and second internal clocks fclkt2 and rclkt2 are in the shape of pulse.
At an initial operation, the second internal clock rclkt2 passes through the second delay line 140 having an initial delay amount and the delay model circuit 190 having a predetermined delay amount. That is, after delayed by the second delay line 140 and the delay model circuit 190, the second internal clock rclkt2 is converted into a feedback clock fb_clk.
The phase comparator 170 compares a phase of the second internal clock rclkt2, used as a reference signal, with that of the feedback clock fb_clk output from the delay model circuit 190 to thereby output the comparison result. In response to an output signal of the phase comparator 170, the delay controller 180 controls delay amounts of the first and second delay lines 130 and 140.
Thereafter, the phase comparator 170 compares a phase of the second internal clock rclkt2 with that of the feedback clock fb_clk having a controlled delay amount based on the comparison result, periodically. When there is a minimum jitter between the second internal clock rclkt2 and the feedback clock fb_clk, a delay locking state of the DLL is accomplished.
The first clock buffer 110 of the DLL is controlled by the clock enable signal cke. That is, in a precharge power-down mode during which the clock enable signal CKE is inactivated as a logic level low, the first clock buffer 110 is disabled although the second clock buffer 120 is enabled. As a result, power consumption caused by unnecessary toggling of the first internal clock fclkt2 is decreased.
For minimizing current consumption of the DLL during the precharge power-down mode, it is preferred that the second clock buffer 120 is also turned off. However, if the second clock buffer 120 is turned off during the precharge power-down mode, operation reliability of the semiconductor memory device cannot be guaranteed. If a precharge power down mode starts before 200 clock cycles after a self refresh operation is terminated (herein, 200 clock cycles is generally required for a delay locking state of the DLL), the delay locking state is not achieved and the second clock buffer 120 for generating a reference clock is turned off; finally, after 200 clock cycles after the self refresh operation is terminated, the DLL included in the semiconductor memory device cannot achieve the delay locking state.
Therefore, during the precharge power down mode, the second clock buffer 120 should be turned on; accordingly, current consumption of the DLL during the precharge power-down mode is not decreased.